1. Field of the Invention
The present invention relates to the manufacturing of integrated circuits.
2. Discussion of the Related Art
Technology, as it advances, provides more and more complex integrated circuits integrating a great number of components of different types, particularly, CMOS transistors and bipolar transistors. The conventional forming of such structures necessitates a large number of manufacturing steps due to the fact that steps specific to the manufacturing of bipolar transistors must be added to the manufacturing steps of a CMOS circuit.
It is thus a constant object of research in the field of integrated circuit manufacturing to search for manufacturing methods enabling simultaneous optimization of components of different types while minimizing the number of manufacturing steps. In particular, it is desired to make the largest possible number of steps common when manufacturing bipolar transistors and MOS transistors on an integrated circuit.
The present invention aims at the simultaneous manufacturing of bipolar and MOS transistors on an integrated circuit in which a large number of manufacturing steps of the bipolar transistors remain common with the MOS transistor manufacturing steps.
More specifically, the present invention aims at the manufacturing of an emitter of a bipolar transistor similarly to the manufacturing of the gate of a MOS transistor.
More generally, the present invention aims at forming a contact between a doped polysilicon layer and an underlying substrate, despite the presence of a thin insulating layer between them.
To achieve these and other objects, the present invention provides a method for manufacturing a contact between a semiconductor substrate and a doped polysilicon layer deposited on the substrate with an interposed insulating layer, in which elements adapted to making the insulating layer permeable to the migration of dopants from the polysilicon layer to the substrate are implanted through the polysilicon layer.
According to an embodiment of the present invention, the insulating layer is a silicon oxide layer.
According to an embodiment of the present invention, said elements are formed of hydrogen.
According to an embodiment of the present invention, said elements are formed of silicon or germanium.
The present invention also provides a method for manufacturing the emitter area of a bipolar transistor in a CMOS-type integrated circuit wafer, including the steps of forming, on the wafer, an insulating layer topped with a polysilicon layer over the entire integrated circuit; in the bipolar transistor area, implanting through the polysilicon layer elements adapted to making the insulating layer permeable to the migrating of dopants from the polysilicon layer; and removing the polysilicon layer and the insulating layer outside of locations where the emitter of the bipolar transistor and the gates of the MOS transistors are desired to be formed.
According to an embodiment of the present invention, the insulating layer is a silicon oxide layer.
According to an embodiment of the present invention, the implantation step includes the implantation of silicon or germanium.
According to an embodiment of the present invention, the implantation step includes the implantation of hydrogen.
The present invention also aims at a method for manufacturing a bipolar transistor in an integrated circuit of CMOS type, including the steps of forming, in the integrated circuit substrate, a region adapted to forming the collector area of the bipolar transistor; implanting in the region a doped region adapted to forming the base of the bipolar transistor; and forming the emitter of the bipolar transistor by the previously mentioned method.
The present invention also aims at a method for manufacturing the emitter area of a bipolar transistor in a CMOS-type integrated circuit, including the steps of implanting, in the bipolar transistor area, an element able to prevent formation of an electrically insulating zone on the said bipolar transistor area; forming an insulating area over the entire integrated circuit; and removing the polysilicon layer and the insulating area outside of the locations where the bipolar transistor emitter and the MOS transistor gates are desired to be formed.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.